1. Field of the Invention
The present invention relates to a method for manufacturing a nonvolatile memory device, and more particularly, to a method for manufacturing a nonvolatile memory device which can prevent damage to a silicon substrate and reduce a number of process steps by forming a logic gate electrode and cell control gate electrode at the same time instead of an SAE etching process.
2. Description of the Related Art
Nonvolatile memory devices are a type of semiconductor memory that can preserve stored data even if its power supply is interrupted. Of these nonvolatile memory devices, an EEPROM (electrically erasable and programmable read only memory is a nonvolatile memory device capable of stable storage even if there is no power supply, and also is a modified erasable and programmable read only memory (EPROM) having the characteristic of electrically erasing stored data and rewriting the same. Thus, the EEPROM can be used conveniently in various applications requiring program rewriting.
The EEPROM can write and erase data by electrically changing the charge of a device constituting a chip, and can reprogram data in a state stored in the system since it is capable of electrical reading and writing. In the EEPROM, a programming operation is enabled by generating channel hot electrons at a drain side, accumulating the electrons in a floating gate electrode and increasing the threshold voltage of a cell transistor, and an erasing operation is enabled by generating a high voltage between a source/substrate and the floating gate electrode, emitting the electrons accumulated in the floating gate electrode and decreasing the threshold voltage of the cell transistor.
In order to have the EEPROM cell to do the write/erase operations of byte (8 bits) unit, it is necessary that a unit cell have one select transistor. The select transistor used is defined simultaneously with the floating gate electrode of an EEPROM cell utilizing a first polysilicon.
Of the EEPROM, a device having a small chip size and having excellent write and erase characteristics includes a flash memory. In case of a flash cell, the flash cell has no select gate, thus it is capable of only block or chip unit erasing. A floating gate electrode defined as a first polysilicon is etched on a field oxide film. Thus, after the deposition of a second polysilicon, the loss of the field oxide film occurs even if the first polysilicon and the second polysilicon are stacked and etched, thereby causing no damage on the silicon substrate.
On the other hand, in case of the EEPROM cell, the select transistor using the first polysilicon and the floating gate electrode of the EEPROM cell are formed in an active region unlike a flash memory. Thus, the active region is opened where no first polysilicon exists in the self align etch (SAE) process of the first polysilicon and the second polysilicon. Due to this, the damage of the active open region by the over-etching of silicon occurs as much as the first polysilicon etching target.
Hereinafter, the problems of the method for manufacturing a nonvolatile memory device according to the conventional art will be described with reference to the accompanying drawings.
FIG. 1 is a sectional view showing an EEPROM device and a logic device formed according to the conventional art.
As shown in FIG. 1, a select transistor 110 formed on the silicon substrate 100, a first polysilicon 121 acting as a floating gate electrode and a second polysilicon 122 acting as a control gate electrode are formed in an EEPROM device region A. Further, a second polysilicon 122′ acting as a logic gate electrode 130 is formed in a logic device region B that is to be formed on the same wafer as the EEPROM device region, thus the logic gate electrode has the same transistor characteristics as a general analog logic device.
FIG. 2 is a plane view showing an EEPROM device and a logic device formed according to the conventional art. An active damage occurs in the process of stacking and etching an EEPROM cell in a C region, and the damage occurred in the active region during the etching process leads to a leakage current. Due to this, a stand-by current is increased, thereby generating a junction leakage current in the drain active side where a contact is to be formed.
FIGS. 3a to 3j are sectional views showing sequential processes for manufacturing a nonvolatile memory device according to the conventional art.
Firstly, as shown in FIG. 3a, a field oxide film 310 is formed on a silicon substrate 300 by a LOCOS method for device isolation, to thus isolate a logic region and an EEPROM cell region. And, a deep N-well and P-well ion implantation are carried out.
Continually, as shown in FIG. 3b, a channel ion implantation of the select transistor and an ion 320 implantation for controlling the threshold voltage of the EEPROM cell are carried out.
Then, as shown in FIG. 3c, a dual gate oxidization process for forming a gate oxide film 330 of the select transistor and a tunnel oxide film 330′ of the EEPROM cell is performed.
Then, a first polysilicon is deposited and a selective photograph and etching process is performed to thus form a gate electrode 340 and a floating gate electrode 340′ of EEPROM cell as shown in FIG. 3d. The first polysilicon is formed in the active region except the field oxide film 310.
Afterwards, as shown in FIG. 3e, in order to insulate the floating gate electrode 340′ of the EEPROM cell and a second polysilicon to be deposited hereinafter, an Oxide-Nitride-Oxide (“ONO”) film 350 is formed on the entire surface of a wafer, and a selective photograph and etching process is performed to completely cover the floating gate electrode 340′.
Then, as shown in FIG. 3f, an ion implantation process for controlling the threshold voltage is performed to a logic device region B and a logic gate oxide film 360 is formed.
Continually, as shown in FIG. 3g, a second polysilicon 370 that is to be used as a control gate electrode of the EEPROM cell and as a gate of the logic device is deposited. Then, as shown in FIG. 3h, the logic device region B is blocked, and the second the polysilicon 370′ of the EEPROM cell region undergoes an SAE (self align etch) process.
Next, as shown in FIG. 3i, the SAE process is, completed to make the first polysilicon/second polysilicon of the EEPROM cell region have a stacked shape. At this time, although there is no problem in the portion where the first polysilicon 340′ exists at the lower end of the second polysilicon 370′, the silicon substrate is exposed at the portion where the first polysilicon 340′ does not exist at the lower end of the second polysilicon 370. Thus, in the SAE process, the silicon substrate is damaged as much as an etching target for etching the ONO film 350 and the first polysilicon 340′ after the second polysilicon etching process. Also, more serious damage occurs in the active region of a D portion where no ONO film 350 exists, thereby giving rise to a leakage current of the EEPROM cell.
Thereafter, as shown in FIG. 3j, the EEPROM cell region A is blocked by photoresist and then the second polysilicon 370 of the logic region is selectively etched to form a logic gate electrode 370″.
According to the method for manufacturing a nonvolatile memory device according to the conventional art, upon the SAE process for the process of forming a gate of a stacked shape of the first polysilicon/second polysilicon in the EEPROM cell, the silicon substrate of the active region at the portion having no first polysilicon, particularly, at the portion having no ONO film, thus giving rise to a leakage current. As a result, there occurs a problem that the standby current is increased to give rise to a leakage current in the drain active side.